1. Field of the Invention
The present invention generally relates to a booting apparatus and a method thereof, in particular, to a booting apparatus which uses a single timer for switching between a plurality of processors and a plurality of memories and a method thereof.
2. Description of Related Art
In recent years, processor speed has been increased dramatically along with the development of information technology. Both Intel and AMD, the two major processor manufacturers, have been focusing in the development of higher-frequency processor in order to gain the leadership in the processor market. Today, the clock cycle of processor has been increased from 100 MHz to 1 GHz. However, along with the increase in the clock cycle of processor, the hardware complexity thereof is also increased, and processor manufacturers have also realized that the speed of processor cannot be increased infinitely, therefore another method has to be adopted to increase the speed of data processing.
Accordingly, a multiprocessor structure has been developed as a new processor technology, wherein a plurality of processors are connected together to achieve the purpose of multi-processing. While booting such a multi-processor system, one of the processors is selected as a bootstrap processor for executing a system booting procedure, and the other processors are considered as application processors and are used for assisting the bootstrap processor. When the system is powered on, each of the processors executes a built-in self-testing function, and if any processor encounters a boot-up error, this processor issues a status flag to notify the system about the error, so that the system can carry out subsequent process. However, if it is the bootstrap processor who encounters an error, an application processor has to be used for replacing the bootstrap processor to carry out the system booting procedure properly.
Conventionally, in the situation mentioned above, a fault resilient booting (FRB) technique is adopted to carry out a resilient booting operation by using a basic input/output system (BIOS), a baseboard management controller (BMC), or other hardware. The conventional FRB technique will be described herein with a system having two processors as example. FIG. 1 is a structural diagram of a conventional dual-processor system which uses a BMC for carrying out FRB, and FIG. 2 is a flowchart illustrating the procedure of the conventional dual-processor system carrying out FRB by using the BMC. First referring to FIG. 1, in the dual-processor system 100, the processor 110 and the processor 120 are respectively connected to the enabling pin 131 and the enabling pin 132 of the BMC 130, wherein the processor 110 is the bootstrap processor. Besides, the BMC 130 is built in with a FRB timer 133 and is connected to a general purpose input/output (GPIO) pin 140 of the BIOS system.
Referring to both FIG. 1 and FIG. 2, a processor for executing the FRB function is preset in the BMC 130 (step S210) before the dual-processor system 100 is powered on. The presetting procedure includes setting a time-out and setting the enabling pins 131 and 132 of the BMC 130 to 1 so that the processor 110 and the processor 120 can be both enabled after the system is powered on. Whenever the system 100 is powered on or reset (step S220), the FRB timer 133 of the BMC 130 is started for counting down the time-out (step S230), and meanwhile, it is determined whether a disabling signal is received (step S240). If the BIOS completes a power on self test (POST) successfully, a disabling signal is issued through the GPIO pin 140 to notify the BMC 130 to disable the FRB timer 133, and from here on the processors 110 and 120 of the system 100 can continue with a normal booting procedure (step S250). However, if the bootstrap processor 110 encounters an error during the system booting procedure, which means the system 100 cannot be booted properly, the FRB timer 133 is not disabled by the BIOS system. Thus, when it is determined that the countdown of the time-out by the FRB timer 133 has been finished (step S260), the BMC 130 switches off the processor 110 by setting the enabling pin 131 to 0 (step S270) and then resets the system 100 to boot up the system again with the processor 120 as the bootstrap processor (step S280).
The theory described above is also applicable to a dual BIOS read only memory (ROM) technique, wherein the dual BIOS ROM technique refers to a technique of disposing two BIOS ROMs on a motherboard for storing the data of the BIOS. A system using dual BIOS ROMs can avoid failure in system boot-up caused by failure in BIOS upgrading wherein there is dismatch between the BIOS file and the motherboard, altered BIOS file, or power failure during BIOS upgrading.
FIG. 3 is a structural diagram of a conventional dual BIOS ROM system, and FIG. 4 is a flowchart illustrating the operation of the conventional dual BIOS ROM system. First referring to FIG. 3, the BIOS ROM system 300 includes a super I/O (SIO) chip 310. The SIO chip 310 is connected to ROMs 320 and 330 via an address/data line and is respectively connected to the ROMs 320 and 330 via a selection pin 311, wherein it is assumed that the ROM 320 is for booting the system while the ROM 330 is used as a standby. Here the signal sent by the selection pin 311 is 1 so that the ROM 320 is enabled, and the signal is then inversed by an inverter 340 and sent to the ROM 330 to disable it. In addition, a ROM timer 312 is disposed in the SIO chip 310 for selecting either the ROM 320 or the ROM 330 for reading the BIOS.
Referring to both FIG. 3 and FIG. 4, after the system 300 is powered on or reset (step S410), the ROM timer 312 starts to count down the time-out (step S420), and meanwhile, it is determined whether a timer disabling signal is received (step S430). If the BIOS can execute a POST normally, then similarly, a disabling signal is issued through a GPIO pin 350 to notify the SIO CHIP 310 to disable the ROM timer 312. Here the signal output by the selection pin 311 is not affected and the ROM 320 is still used for booting the system (step S440). However, if an error occurs to the ROM 320 during the system booting procedure, the BIOS cannot boot the system normally and accordingly cannot disable the ROM timer 312. When it is determined that the countdown of the time-out has been completed (step S450), the ROMs are switched (step S460), and the signal sent by the selection pin 311 is set to 0, so that the ROM 320 is disabled and the ROM 330 is enabled. Finally, the system is reset and the ROM 330 is used for booting the system (step S470).
As described above, the multiple processor system and the dual BIOS ROM system respectively use a timer for processor switching or BIOS ROM switching. If the two set different time-outs and an error occurs during the system booting procedure, the system may be reset once the countdown of the time-out at either party (for example, the processors) is completed but before finding out which party has caused the error (for example, the BIOS ROMs), thus, system misjudgement may be caused. For example, assuming that the time-out of the processors is shorter than that of the BIOS ROMs, if the processors both work properly during the system booting procedure but the preset BIOS ROM encounters an error, the system misjudges that the processor has caused the error and then resets the system since the timer of the processor completes the countdown first. In this case, the system will never be able to switch processors or BIOS ROMs and accordingly cannot be booted up successfully.